The SCI to Fastbus interface

Page under construction

Highlights

The Fastbus-SCI link is firmware driven FIFO interface between a CERN Host Interface (CHI) and SCI, using a AMD29200 RISC processor card with DMA controller.

Transfer of data to/from the CHI data memory is done via the I/O port of the module. The 29200 processor controls the data stream between the FIFOs on the CHI side and the the FIFOs on the SCI side. Fourteen SCI packet types are supported.

Detailed description

The hardware of the SCI to Fastbus interface consists partly of already existing, commercial modules, partly of a board that was specially developed by Jon Wikne at the Department of Physics, University of Oslo.

The prototype was built in the summer of 1994. Software development / debugging (by Hans Ludvig Opheim) is still in progress (April 1995).

The system components are:

A block diagram is given below.

The C-bus transaction controller state machine can be clocked at up to 40MHz. However, the practical transfer rate will be limited by the 16MHz clock speeds of the AMD29200 and CHI parts of the system. Benchmarks remain to be obtained.

C-Bus instructions supported in hardware are:

First version of software will NOT implement Cache Coherency.

Here are pictures of the Fastbus/SCI card (with mezzanine and AMD29200 daughter cards) and the complete assembly in the Fastbus crate.

An eventual, later production version will integrate the components on the mezzanine card and the "glue" card on one Fastbus size card.


Jon Wikne, , 10-04-1995