The CACTUS and SIRI Detector Systems (*)

Page under construction

The nuclear physics group in Oslo has developed a technique to study gamma-spectra from specific nuclear excitation energies. The nucleus is populated through one-neutron transfer reactions, where coincidences are made between the charged ejectile and -rays. The aim of these studies is to learn more about nuclear behaviour at excitation energies where statistical properties dominate. The combined CACTUS/SIRI system is a unique coincidence set-up dedicated for these studies.

The CACTUS -detector ball

The CACTUS detector accommodates 27 NaI and 3 Ge -detectors which are fixed to a frame at a distance of 24 cm to the target. The three Ge detectors have efficiencies of 50, 60 and 70 %, respectively. The 5" x 5" NaI(Tl) detectors are equipped with 5" PMT. The crystals are shielded laterally with 2 mm lead and collimated with 10 cm lead in front. The solid angle of each NaI detector corresponds to 0.5 % of the total solid angle. The front of the NaI and Ge detectors are covered with a 2 mm Cu absorber.

The target chamber can be removed from the centre of the NaI ball through the two remaining holes (32 holes in total). Beam focusing can be performed with a piece of quartz at the target place, where the beam spot can be monitored by a TV camera through a Plexiglas window.

The SIRI particle-telescope detector

The SIRI detector consists of an array of silicon particle telescopes for the detection of light charged particles. The telescopes are placed inside the CACTUS detector ball. The detector and read-out chips are user specified, and represents high technology developments.

Each SIRI telescope element consists of one front (E) and one end (E) detector which are sandwich mounted back-to-back on a 1 mm thick ceramic substrate. The front and end detector have the same shape (almost trapezoidal in form) with a total active area of 500 square mm. Each detector element is segmented into 8 parallel pads. The detectors are glued to the ceramic substrate, where separate bonding and cabling for each pad is performed. Surface mounted circuitry is laid on both sides of the substrate to serve the front and end detectors, respectively. The detector elements are connected via flat cables to read-out chips (see below).

The front detector is based on a 0.135 mm thick silicon wafer, so that -particles of around 15 MeV can pass through the detector. The end detector is 2 mm thick, and can stop 70 MeV -particles. The front detector was straightforward to develop, and a typical leakage current for a pad is less than 0.5 nA. For the thick end-detector a multi-guard structure of 2.5 mm is designed around the detector. This is made in order to improve the detector performance with respect to noise, leakage current and overbias capability. The guard give a better uniform field around the pads and decouple the leakage current generated outside the pads from the active detector area. The guard also controls the termination of the depletion region towards the exterior of the detector. The silicon wafer for the end detector is made of very high resistivity (> 10 kcm) silicon substrate.

Eight and eight telescope elements are mounted to form a ring.

Detector rings, associated readout chips and target are mounted on rods along the beam-axis. It will be possible to switch between four targets without breaking the vacuum. The target chamber is designed so that cooling of the chips and detectors can be performed if necessary. New oil free vacuum pumps are installed in connection with the SIRI set-up.

The Read-Out System

For read-out of energies and time, we use a custom designed, monolithic chip (ASIC). Each chip is designed to handle 32 silicon pads. The chip is implemented in AMS 1.2 m BiCMOS, double poly, double metal process. The power consumption is 350 mW, which gives about 6 degrees C increase in temperature when bonded to a CLCC84 chip carrier.

The chip contain preamplifiers, shapers, discriminators, pile-up control and multiplicity. At the first stage a fast preamplifier splits the signal into a time and energy branch. The energy and timing shapers have rise times of 1 s and 25 ns, respectively. The chip gives also hit pattern, which can be read-out by a dedicated 5 bit bus.

After each event the computer ready signal resets the chips except the part concerning multiplicity and pile-up detection. The inspection for pile-up is performed both before and after the event of interest: if two signals arrive within 2 s, the corresponding latch will be reset. Signals less than 100 ns apart cannot be separated. The pile-up function can be externally set on/off.

Generally, only one or possibly two detectors fire per chip. Therefore, the coincidences detected within the chip are handled using a summing technique (multiplicity) of the logic timing signals. The multiplicity signal is a linear sum of the logical signals from all detectors. The signal can be used to make multiplicity requirements or fast coincidences with other types of detectors. In this way, reset (within 1 s) can be performed at an early stage for bad events.

The Data Acquisition System

The chips will be connected to each other on a common bus within the target chamber. Outside the chamber the bus is connected to a read-out controller (ROCO) containing ADC's and data buffers. Thresholds, widths and logical signals are computer controlled via the ROCO.

The data acquisition system is built around a SparcStation 10/512, with an interface (Bit3) to the VME crate where a single board computer takes care of the event builder process. The data transfer system is designed to give a fast data stream out on exabyte cartridge. Recently, a new graphic oriented (X-windows) acquisition system (SIRIUS) and data analysing tools (MAMA) have been developed.

Here is a more elaborate description of the data acquisition system, also including the parts not directly related to SIRI.

(*) This project is funded by the Norwegian Research Council (NFR). The silicon detectors and the design of the ASIC chips were performed by SINTEF in Oslo. The ASIC chips were processed by AMS in Austria. The mounting of the circuitry and detectors on ceramic substrates is made by Microcomponent in Horten.

Last update 11-07-1996 by Jon Wikne,